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Implementation of Data Compression Algorithms on Fpga Using Soft-Core Processor

Vijay G. Savani, Piyush M. Bhatasana, Akash I. Mecwan

With the increase in the requirement of online real time data, data compression algorithms are to be implemented for increasing throughput. This paper describes the methods of creating dedicated hardware which can receive uncompressed data as input and transmit compressed data at the output terminal. This method uses FPGA for the same, wherein the hardware part has been created using Xilinx Embedded Development Kit (EDK) and data compression algorithms have then been implemented on the same hardware. The EDK helps creating a Soft Core Processor on the FPGA with desired specifications. The data compression algorithm can be implemented on this processor. The advantage of this kind of a system is that, without changing the hardware, the FPGA can be reprogrammed with a new algorithm whenever a better technique is discovered. For the proof of concept the Huffman coding technique has been implemented. The Soft Core Processor uses serial port and for direct input the GPIO of the processor were used. The user enters text data through this port, and the soft core processor using Huffman’s data compression algorithm gives compressed data as the output.